STA Design Intern (Semiconductors)

TL;DR

STA Design Intern (Semiconductors): Evaluating timing margins of semiconductor logic designs for ASIC/SoC to ensure target speed functionality with an accent on static timing analysis and constraint management. Focus on analyzing slack, fixing setup/hold violations, and developing scripts to optimize EDA flows.

Location: Hybrid in Ho Chi Minh City, Vietnam (Must be able to work onsite 4 days per week)

Company

A global leader in semiconductor design and manufacturing through the Silicon and Platform Engineering Group.

What you will do

• Perform Static Timing Analysis (STA), including kicking off runs and implementing timing fixes.
• Assist in creating, updating, and debugging timing exceptions and constraints.
• Develop scripts using Tcl, Python, or Perl to enhance and speed up existing flows.
• Analyze slack and resolve setup/hold violations to ensure chips function at target speeds.

Requirements

• Bachelor's student (3rd or Final year) in Electrical Engineering, Computer Engineering, VLSI Systems, Physics, or Mathematics.
• Must be able to work onsite 4 days per week in Ho Chi Minh City.
• Commitment to at least a 6-month internship program.
• Foundational knowledge of digital logic, flip-flops, clock domains, and CMOS circuit design.
• Proficiency in scripting languages (Tcl, Python, or Perl) and HDL (Verilog or SystemVerilog).
• English: Strong verbal and written communication skills (B2+).

Nice to have

• Familiarity with Linux environments.
• Basic exposure to EDA tools.

Culture & Benefits

• Competitive internship allowance and lunch allowance.
• Access to structured training programs and involvement in multinational projects.
• Employee sports and extracurricular programs.
• Comprehensive shuttle bus system covering Ho Chi Minh City, Binh Duong, and Dong Nai.
• Safe, stable, and dynamic working environment with high-quality facilities.