Senior/Staff Frontend Engineer (RTL Design)

TL;DR

Senior/Staff Frontend Engineer (RTL Design): Designing and implementing microarchitectures for ASIC chips with an accent on Verilog HDL, VLSI design, and IP integration. Focus on GPGPU/NPU/CPU module design, including memory subsystems and tensor processor cores.

Location: Singapore, SG / Penang, MY

Company

hirify.global is a world-leading technology company specializing in Bitcoin mining solutions and AI cloud capabilities.

What you will do

• Participate in architectural design discussions.
• Implement microarchitectural designs using Verilog HDL based on architectural specifications.
• Perform design reviews and maintain delivery quality control.
• Identify, select, and integrate soft and hard IP.
• Collaborate with verification and emulation teams to develop test plans and debug.
• Work with the implementation team to close design on synthesis, timing, and power.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• 3-5+ years of experience in RTL design for ASIC with tape-out experience.
• Strong understanding of computer architecture and VLSI design.
• Experience in GPGPU, NPU, or CPU module design (e.g., work schedulers, memory subsystems, vector or tensor processor cores).

Culture & Benefits

• Inclusive environment that values authenticity and diversity of thoughts.
• Fast-growing company with an exciting start-up spirit.
• Opportunity to network with industry pioneers and impact the digital asset industry.
• High degree of personal accountability, autonomy, and growth opportunities.
• Attractive welfare benefits, including training and mentoring.