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7 дней назад

Senior USB IP Design Verification Engineer (USB)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Senior USB IP Design Verification Engineer (USB/SystemVerilog): Ensuring the functionality and quality of USB IP designs through the development of functional verification plans and test benches with an accent on RTL design verification and UVM/OVM methodologies. Focus on executing verification strategies, debugging presilicon environments, and optimizing test coverage for high-speed IO IPs.

Location: Hybrid in Penang or Kulim, Malaysia

Company

hirify.global is a global leader in creating world-changing technology and silicon solutions that define the next generation of computing experiences.

What you will do

  • Develop functional verification plans and test benches to ensure comprehensive coverage of microarchitecture specifications.
  • Execute verification strategies through system simulation models to analyze power, timing, and functionality.
  • Implement corrective measures and debug issues within the presilicon environment.
  • Collaborate with architects, RTL developers, and physical design teams to validate complex architectural features.
  • Maintain and improve functional verification infrastructure and methodologies to support innovation.
  • Document test plans and lead technical reviews with design and architecture teams.

Requirements

  • Bachelor's degree in Electrical, Electronics, Computer Engineering, or Computer Science.
  • 6-8 years of industry experience in RTL design verification.
  • Expertise in System Verilog and UVM/OVM methodologies.
  • Proficiency in designing test plans, testbench infrastructure, coverage points, and assertion checks.
  • Experience with pre-silicon tools such as VCS/Synopsys and scripting languages like Python, Perl, or Shell.
  • Understanding of high-speed IO IPs (USB, PCI Express, AMBA) and VLSI design flows.

Nice to have

  • Advanced degree (Master's or PhD) in a relevant field.
  • Experience with SoC-level validation environments and subsystem interoperability.
  • Expertise in power-aware design and simulation for low-power architecture.

Culture & Benefits

  • Hybrid work model allowing split time between on-site and off-site work.
  • Opportunity to work within the Silicon and Platform Engineering Group on breakthrough silicon solutions.
  • Collaborative environment working with diverse, cross-functional teams.
  • Commitment to ethical hiring practices and RBA compliance.

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