Lead Design Engineer (ASIC)

TL;DR

Lead Design Engineer (ASIC): Implementing physical design projects including floor planning, P&R, and timing closure with an accent on low power and high speed designs at the latest technology nodes. Focus on leading next-generation physical design methodology development and ensuring successful tapeouts.

Location: GYEONGGI-DO (Seoul)

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware solutions for the semiconductor and electronics industries.

What you will do

• Perform full-cycle physical design implementation, including floor planning, power grid design, place and route (P&R), and clock tree synthesis.
• Execute timing closure, power/signal integrity signoff, and physical verification (DRC/LVS/Antenna).
• Handle EM/IR signoff and DFM Closure for complex designs.
• Develop low power and high speed designs at the latest technology nodes.
• Participate in or lead the development of next-generation physical design methodologies and flows.
• Collaborate closely with the RTL design team to ensure successful tapeouts.

Requirements

• 9+ years of experience with ASIC design flow and hierarchical physical design strategies.
• Deep understanding of sub-micron technology issues.
• Solid knowledge of Low Power Design, DFT, static timing analysis (STA), and closure.
• Expertise in data skew balancing, duty cycle adjustment, and EM/IR-Drop/crosstalk analysis.
• Ability to work independently and be hands-on at all levels of design verification and testing.
• English: Good communication skills required