Senior/Staff Front-End Engineer (PCIe)

TL;DR

Senior/Staff Front-End Engineer (PCIe): Develop and implement Verilog RTL for PCIe-related IP blocks and support verification closure with an accent on pre-silicon and post-silicon debug. Focus on designing robust high-quality IP solutions, optimizing PCIe integration, and ensuring 100% functional coverage.

Location: Singapore / Malaysia

Company

hirify.global is a world-leading technology company specializing in Bitcoin mining solutions and AI cloud infrastructure.

What you will do

• Implement Verilog RTL for IP sections, focusing on PCIe integration, configuration, and performance evaluation.
• Ensure verification closure by achieving 100% functional coverage.
• Conduct design verification and debug issues across both pre-silicon and post-silicon stages.
• Collaborate with and support software development teams.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 5+ years of experience in semiconductor or high-technology R&D.
• Proven experience in Verilog RTL development within an SoC/IP environment.
• Strong technical understanding of PCIe architecture and logic design.
• Proficiency in scripting languages such as Perl, Shell, or TCL for design automation.

Culture & Benefits

• Inclusive environment that values authenticity and diversity of thought with a startup spirit.
• Opportunity to network with industrial pioneers and impact the digital asset industry.
• High degree of personal accountability, autonomy, and fast professional growth.
• Attractive welfare benefits, including specialized training and mentoring programs.