ASIC Layout Designer (RF)

TL;DR

ASIC Layout Designer (RF): Responsible for block and chip-level layout of high-performance RF Analog ASICs with an accent on parasitic minimization, signal path optimization, and complex matching techniques. Focus on ensuring outstanding product flow from development to mass production, including test time reduction and yield improvement.

Location: Must be based in Boulder, CO, United States

Salary: $103,500–$191,900

Company

hirify.global is an independent public company driving innovation in precision technology, empowering engineers to build next-generation breakthroughs through high-performance instruments and subsystems.

What you will do

• Perform layout of cells, blocks, and chips in CMOS, BiCMOS, and Bipolar processes.
• Manage chip-level assembly, verification, and debugging.
• Plan and lead layout teams, including contractors and teammates.
• Develop and train on layout tools while troubleshooting software and PDKs.
• Drive top-down abstraction and black-box methodology for project database management.

Requirements

• Minimum 7 years of experience in RF/Analog/Mixed Signal layout design.
• Must be a U.S. Person (citizen, permanent resident, or protected individual) due to ITAR regulations.
• Proficiency in broadband RF/high-speed layout, sensitive RF analog matching, and parasitic minimization.
• Expertise in Cadence Virtuoso, physical verification tools (Calibre, PVS, Pegasus), and scripting (Python, Skill, Shell).
• Strong understanding of electromigration, common-centroid matching, and differential pairs.

Culture & Benefits

• Competitive compensation package including bonus eligibility.
• Opportunity to work on mission-critical advancements across various industries.
• Commitment to an inclusive and diverse work environment.
• Support for professional growth and mentoring within a collaborative team.