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3 дня назад

Principal RTL Design Engineer (ASIC)

86 000 - 186 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Principal RTL Design Engineer (ASIC): Designing and implementing high-performance analog, digital, and mixed-signal IP for wireline applications with an accent on DDR and flash controller/PHY subsystems. Focus on the full ASIC development lifecycle, including RTL design, verification, STA timing closure, and silicon bring-up in the lab.

Location: Onsite in Burnaby, Canada

Salary: $86,000–$186,000

Company

A global semiconductor leader providing innovative technology that powers electronic systems worldwide.

What you will do

  • Participate in the full ASIC design cycle, from initial design and verification to backend implementation and silicon debugging.
  • Design RTL using Verilog/SystemVerilog and implement critical logic such as clock/reset, Jtag, DFT, and SRAMs.
  • Perform clock domain crossing (CDC) analysis, lint checks, and power simulations to ensure design quality.
  • Collaborate with verification teams to review and execute verification plans and debug simulation issues.
  • Work with backend teams to resolve STA timing issues and analyze critical paths through trial synthesis.
  • Develop C-based drivers for DDR/Flash PHY and provide debug support during lab-based silicon bring-up.

Requirements

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering/Science, or a related field.
  • 2–10 years of professional ASIC development experience.
  • Strong proficiency in RTL design and verification using Verilog, SystemVerilog, or VHDL.
  • Hands-on experience debugging hardware with oscilloscopes and logic analyzers.
  • Knowledge of C/C++ and scripting languages such as Python, Perl, TCL, or Shell.
  • Must be based in or able to work onsite in Burnaby, Canada.

Nice to have

  • Working knowledge of DDR and Flash Controller/PHY/memory architectures.

Culture & Benefits

  • Comprehensive compensation including base pay, restricted stock units (RSUs), and quarterly bonuses.
  • Health benefits starting on day one of employment.
  • Retirement savings plans and an industry-leading IESPP program with a 6-month look-back feature.
  • Access to Leadership Passage Programs to support long-term career growth and stability.
  • Culture based on trust, empowerment, diversity, and values-based decision making.

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