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5 дней назад

Junior Physical Design Engineer (CPU)

105 650 - 149 150$
Формат работы
onsite
Тип работы
fulltime
Грейд
junior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Junior Physical Design Engineer (CPU): Supporting the implementation of next-generation CPU cores from RTL to GDS with an accent on synthesis, place and route, and physical verification. Focus on optimizing timing and power while ensuring design rule compliance for high-performance silicon.

Location: On-site in Hillsboro, Oregon, US

Salary: $105,650–$149,150 USD

Company

hirify.global is a global leader in semiconductor design, developing CPU cores for client, server, IoT, and AI platforms.

What you will do

  • Support physical design execution for CPU core or subsystem blocks under guidance.
  • Assist with synthesis, place and route (PnR), and physical verification tasks.
  • Perform analysis for timing, power, and design rule compliance.
  • Debug and resolve design issues with mentorship from senior engineers.
  • Contribute to script and flow development using TCL and Python.
  • Collaborate with cross-functional teams including RTL design, verification, and full-chip integration.

Requirements

  • Bachelor's in Computer/Electrical Engineering (2+ years exp) or Master's in the same field (3+ months exp).
  • Experience with IC design tools (Synopsys/Cadence) for logic synthesis, place and route, and static timing analysis.
  • Knowledge of PV convergence and physical design verification (DRC/LVS, Noise, and electro-migration checks).
  • Proficiency in TCL and at least one other interpreted language (e.g., Python, Perl, Ruby).
  • Experience with synthesis of a digital logic block integrated into a large SoC or IP.
  • Must be based in or able to work on-site in Hillsboro, Oregon.

Nice to have

  • Knowledge of physical design best practices for floor-planning, routing techniques, and clock distribution.
  • Expertise in Static Timing Analysis, Noise analysis, and reliability verification.
  • Experience with RTL to GDS methodologies and formal equivalence.
  • Familiarity with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus).

Culture & Benefits

  • Competitive total compensation package including stock bonuses.
  • Comprehensive benefits including health, retirement, and vacation programs.
  • Opportunity to work on cutting-edge CPU designs powering AI and IoT platforms worldwide.
  • Collaborative culture that values inclusion, diverse perspectives, and continuous learning.

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