Senior Design Engineer (CAD & Methodology) (ASIC)

TL;DR

Senior Design Engineer (CAD & Methodology) (ASIC): Developing and optimizing EDA tool flows and design methodologies for high-performance ASIC hardware with an accent on tool automation and silicon performance. Focus on refining physical design infrastructure, creating robust automation scripts, and maximizing cryptographic efficiency.

Location: San Jose, CA

Company

hirify.global is a world-leading technology company for AI and Bitcoin mining infrastructure.

What you will do

• Own, develop, and maintain advanced digital and analog implementation flows for seamless EDA tool integration.
• Optimize Cadence ADE and digital implementation suites to maximize engineer productivity and silicon performance.
• Drive and refine digital implementation flows using Cadence Innovus or OpenROAD, focusing on floorplanning and timing closure.
• Create and maintain robust automation scripts and internal tools using TCL, Python, BASH, and C.
• Partner with analog and digital circuit designers to troubleshoot complex tool anomalies and flow failures.
• Tailor design constraints and flow priorities toward cryptographic efficiency based on the Bitcoin ecosystem.

Requirements

• Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Proven hands-on experience in the integrated circuit (IC) design industry.
• Deep understanding of Cadence ADE architecture and environment customization.
• Production-level familiarity with Cadence Innovus or the OpenROAD framework.
• Fluency in TCL, Python, BASH, and C/C++.
• Solid understanding of Bitcoin mining, cryptographic hashing, and ASIC-boost optimization.