Senior FPGA RF Signal Processing Engineer (Embedded)

TL;DR

Senior FPGA RF Signal Processing Engineer (Embedded/RF): Implementing HDL for digital signal processing of RF systems on FPGAs with an accent on real-time execution, SDR, and high-performance wireless communication. Focus on designing and optimizing DSP algorithms for communications, ESM, and radar applications.

Location: Hybrid (Must be based in Mountain View, CA, working on-site 3 days per week)

Salary: $138,000 - $190,000

Company

An end-to-end Space Systems Provider that designs, builds, and operates LEO satellite constellations delivering mission-critical Earth Intelligence.

What you will do

• Implement and optimize DSP algorithms on FPGAs for real-time execution.
• Prototype algorithms in Python and port them to ARM SoCs.
• Design and simulate DSP algorithms for RF applications, including Communications, ESM, and Radar.
• Collaborate with RF hardware engineers on instrument bring-up, calibration, and system integration.
• Author technical documentation, design specifications, and test reports.

Requirements

• 5+ years of professional experience in FPGA development of RF DSP.
• Profound expertise in HDL (Verilog, System Verilog, VHDL) and FPGA system architecture.
• Strong knowledge of RF digital signal processing techniques (spectrum monitoring, modulation/demodulation, filtering).
• Must be a U.S. person (citizen, green card holder, etc.) to comply with ITAR/EAR regulations.
• Ability to acquire and maintain a security clearance.

Nice to have

• Experience with Xilinx/AMD RFSoC or MPSoC.
• Proficiency in C/C++ or Rust for embedded/real-time systems.
• Experience with space-based applications.
• Exposure to CI/CD pipelines for embedded firmware.

Culture & Benefits

• Competitive equity grants and comprehensive benefits package.
• Medical, dental, and vision insurance.
• 401k retirement plan.
• 3 weeks paid vacation, 12 paid holidays, and unlimited sick time.
• Paid parental leave.