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1 день назад

Senior/Staff Frontend Design Engineer (RiscV)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Singapore/Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR

Senior/Staff Frontend Design Engineer (RiscV): Integration of commercial RISC-V core soft IP with external accelerators with an accent on CPU core customization and RTL modification. Focus on optimizing PPA requirements, driving ASIC front-end implementation, and debugging complex logic issues.

Location: Singapore / Malaysia

Company

hirify.global is a world-leading technology company for Bitcoin mining and AI cloud.

What you will do

  • Integrate commercial RISC-V core soft IP with external accelerators using custom extension instruction interfaces.
  • Perform feature tailoring of CPU soft IP to meet strict performance, power, and area (PPA) requirements.
  • Conduct targeted Verilog/SystemVerilog RTL design modifications, focusing on the processor front-end and control path.
  • Collaborate with performance, middle-end, and back-end engineers to optimize system-level performance and physical design.
  • Drive ASIC front-end implementation, including synthesis, static timing analysis (STA) closure, and power reduction.
  • Contribute to design verification (DV) and debug complex logic issues in pre-silicon and post-silicon stages.

Requirements

  • Degree in Electrical Engineering, Computer Engineering, or Computer Science with a strict focus on computer architecture.
  • Deep familiarity with RISC-V ISA, custom extensions, privilege modes, and CSRs.
  • Hands-on experience in CPU core integration, technical specification drafting, and IP feature tailoring.
  • Extensive Verilog RTL development experience using industry-standard tools.
  • Proven experience collaborating with performance modeling and P&R (back-end) engineering teams.
  • Proficiency in scripting languages such as Python, Perl, Shell, or TCL for design automation.

Nice to have

  • Knowledge of synthesis flows, linting, CDC/RDC analysis, and static timing analysis (STA).
  • Experience with SoC-level power-saving, clocking architectures, and low-power microarchitecture.
  • Familiarity with DFT, DFX, and MBIST techniques.

Culture & Benefits

  • Culture that values authenticity and diversity of thought.
  • Inclusive environment with an exciting start-up spirit.
  • Opportunity to network with industrial pioneers in the digital asset industry.
  • High degree of personal accountability, autonomy, and fast growth opportunities.
  • Attractive welfare benefits, including professional training and mentoring.

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