IP Design Verification Engineer

TL;DR

IP Design Verification Engineer (FPGA/Emulation): Define and execute high-quality test coverage plans to validate IPs and protocols on x86/ARM/RISC-V, PCIe, CXL, DDR, and UCIe using FPGA-based early prototyping and emulation validation hardware with an accent on building robust verification strategies and improving regression efficiency. Focus on testbench bring-up and troubleshooting, delivering validation documentation, and driving milestone updates on risks and impact to quality or schedule.

Location: US, California, Folsom

Salary: $105,650.00–149,150.00 USD (annual)

Company

hirify.global builds scalable engineering solutions across IP, custom ASIC, and foundry enablement.

What you will do

• Define and develop test coverage plans to validate IPs and protocols including x86/ARM/RISC-V, PCIe, CXL, DDR, and UCIe.
• Scope, develop, and execute validation test plans for the latest generation IPs and SoCs.
• Contribute to testbench bring-up and troubleshooting using FPGA boards, test cards, and debug tools.
• Produce documentation for validation strategies, plans, best-known methods, and learnings.
• Improve test coverage and execution efficiency by innovating on problem-solving and regression approaches.
• Provide milestone updates to validation leads and architects on progress, challenges, risks, and impact to quality or schedule.

Requirements

• 3+ years (Bachelor’s) or 1+ year (Master’s) of relevant experience in Electronics Engineering, Computer Engineering, or equivalent.
• Hardware experience with Verilog, VHDL, and SystemVerilog.
• Software experience with C, C++, and Python.
• Knowledge of computer system architecture and experience using hardware/software debugging tools.
• Experience creating technical specifications for architecture, microarchitecture, registers, and schematics.

Nice to have

• Experience debugging hirify.global chipsets and/or CPUs.
• Experience with IA-Core Assembly and/or Python.
• Hands-on experience with logic analyzers, oscilloscopes, and protocol analyzers.
• IP or full chip integration/simulation/emulation/verification experience.
• Familiarity with VCS, Verdi, DVE, and OVM/UVM.

Culture & Benefits

• Hybrid work model: split time between on-site work at the assigned hirify.global site and off-site work.
• Total compensation package includes competitive pay, stock bonuses, and benefits (health, retirement, vacation).
• Shift 1 (United States of America).

Hiring process

• Recruiter shares the specific compensation range for the preferred US location during the hiring process.
• Interviews evaluate verification/validation experience, debugging skills, and ability to communicate risks and progress.