Sr. Staff Software/Firmware Engineer (MCU Development)

TL;DR

Sr. Staff Software/Firmware Engineer (MCU Development): Developing and integrating RISC-V MCU subsystems for high-speed SerDes IP validation with an accent on bare-metal firmware, boot flows, and system-level bring-up. Focus on implementing calibration algorithms and building scalable software-driven closed-loop validation frameworks.

Location: Santa Clara, CA

Salary: $131,010 - $196,300 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Lead integration of RISC-V cores into chip validation environments, defining memory maps, boot flows, and execution environments.
• Develop bare-metal and RTOS-based firmware for PHY/IP control, including calibration, training, and tuning algorithms.
• Drive silicon and pre-silicon bring-up, performing root-cause analysis for system-level failures across hardware and firmware.
• Integrate RISC-V firmware into PHY validation automation frameworks for simulation, emulation, and FPGA.
• Transition validation methodology from directed external tests to software-driven closed-loop validation.
• Maintain the RISC-V toolchain environment, including GCC, linker scripts, and debug infrastructure.

Requirements

• 8+ years of experience in embedded systems, firmware, or SoC development.
• Strong proficiency in C/C++ with expertise in bare-metal programming.
• Experience with low-level system development: boot flows, startup code, linker scripts, and register-level programming.
• Hands-on experience debugging HW/SW integration issues on silicon, FPGA, or RTL simulation.
• Solid understanding of computer architecture fundamentals, including CPU, memory hierarchy, and buses.
• Must be eligible to access export-controlled information under U.S. law.

Nice to have

• Experience with RISC-V systems or ARM Cortex-M architectures.
• Familiarity with AHB/AXI-lite bus fabrics and interrupt systems like PLIC and CLINT.
• Experience with PHY, SerDes, or high-speed IP bring-up and validation.
• Knowledge of RTOS such as FreeRTOS or Zephyr.
• Exposure to hardware verification environments (UVM, testbenches) or simulation/emulation workflows.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive financial well-being and family support programs.
• Robust mental and physical health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.