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2 дня назад

Test Chip Designer (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Vietnam
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR

Test Chip Designer (Semiconductor): Leading the end-to-end design, fabrication, and silicon validation of test vehicles for standard cell libraries and memory compilers with an accent on physical implementation and silicon characterization. Focus on architecting silicon experiments, managing tapeout lifecycles, and correlating silicon measurements with pre-silicon models to ensure IP quality.

Location: Danang, Vietnam (Onsite)

Company

Mixel, a hirify.global Company, is an innovator of high-performance analog mixed-signal semiconductor IPs powering applications in mobile, automotive, AI, and VR/AR.

What you will do

  • Define test chip architecture, floorplans, and silicon experiment plans for library and memory compiler characterization.
  • Own the full physical implementation flow including synthesis, place and route, timing closure, and physical verification.
  • Develop DFT strategies and ATE test programs for silicon validation and measurement.
  • Lead silicon bring-up in the lab, debug functionality, and establish stable measurement environments.
  • Analyze silicon data against pre-silicon models and author formal reports documenting findings and recommendations.
  • Manage project schedules, budgets, and risk registers while coordinating across cross-functional teams.

Requirements

  • BS, MS, or PhD in Electrical or Computer Engineering.
  • 5+ years of industry experience in digital/mixed-signal IC design.
  • Proven track record of taking at least one full test chip from concept through silicon report.
  • Deep expertise in standard cell library architecture, characterization, and memory compiler design.
  • Hands-on experience with digital implementation flows (synthesis, P&R, STA, physical verification).
  • Strong scripting skills in Python, TCL, or Perl within Linux environments.

Nice to have

  • Experience with advanced process nodes (7nm, 5nm, 3nm).
  • Background in correlating silicon measurements to SPICE and aging models.
  • Prior leadership experience in multi-engineer test chip programs.
  • Experience interfacing directly with foundry partners and customers.

Culture & Benefits

  • Focus on technical innovation and creative thinking.
  • Collaborative environment with no layers of management.
  • Emphasis on people well-being, mutual trust, and respect.
  • Comprehensive compensation package including potential equity and bonuses.
  • Full range of medical and financial benefits.

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