Staff Engineer, Physical Design (Semiconductor)

TL;DR

Staff Engineer, Physical Design (Semiconductor): Developing and optimizing physical design methodologies for next-generation high-performance processor chips with an accent on block-level PNR and advanced CMOS process nodes. Focus on performing synthesis, timing analysis, and logic ECOs to ensure robust design performance for server and networking applications.

Location: Must be based in Santa Clara, CA

Salary: $111,070–$166,400 per annum

Company

hirify.global is a leading semiconductor company providing essential data infrastructure solutions for cloud, AI, and enterprise architectures.

What you will do

• Maintain and enhance Place and Route flows using industry-standard EDA tools.
• Perform synthesis, place and route, and timing analysis on complex logic blocks.
• Develop and implement timing and logic ECOs to address congestion and timing issues.
• Collaborate with RTL design teams to drive necessary design modifications.
• Debug and resolve block-level timing issues at the partition level.
• Automate design processes and improve workflow efficiency through scripting.

Requirements

• Must be eligible to access export-controlled information under U.S. law.
• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.
• 5+ years of experience in physical design with a focus on block-level PNR.
• Proficiency with EDA tools such as Cadence Innovus/Genus or Synopsys IC Compiler.
• Strong expertise in static timing analysis and EM/IR-Drop/Crosstalk analysis.
• Demonstrated ability to create automation scripts using Tcl or Perl.

Culture & Benefits

• Comprehensive financial well-being programs including an employee stock purchase plan.
• Robust mental health resources and family support programs.
• Recognition and service awards for employee contributions.
• Collaborative environment focused on long-term innovation in data infrastructure.