Analog Layout Principal Engineer (Semiconductor)

TL;DR

Analog Layout Principal Engineer (Semiconductor): Developing High-Speed Connectivity and Broadband Analog products with an accent on high-performance analog circuits in deep sub-micron and FinFET technologies. Focus on top-level integrations, achieving physical verification closure (DRC/LVS), and mentoring layout teams.

Location: Pavia, Italy

Salary: €54,800 – €73,100 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Create layouts for high-performance analog circuits using industry-standard CAD tools in deep sub-micron and FinFET technologies.
• Collaborate with Circuit Design Engineers to realize layout requirements based on schematic functions.
• Coordinate with Physical Verification (PV) teams to resolve DRC, LVS, ANT, ERC, and EMIR issues.
• Lead and mentor a custom analog layout team through the project lifecycle.
• Manage top-level integrations and drive products into volume production.

Requirements

• Bachelor's degree in Electrical Engineering or Computer Science with 15+ years of experience (or Master's with 10-12, PhD with 8-10).
• Proven record of laying out high-performance analog circuits in state-of-the-art CMOS process technologies.
• Expertise in Cadence Virtuoso VXL and/or Synopsys Custom Compiler.
• Proficiency with Mentor Graphics Calibre for DRC/LVS verification.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Culture & Benefits

• Competitive base pay and comprehensive benefits package.
• Collaborative, transparent, and inclusive work environment.
• Opportunity to work with global teams across Argentina, APAC, the U.S., Canada, and Europe.
• Continuous learning and knowledge-sharing culture within a leading semiconductor firm.