Principal Collateral Device Engineer (Semiconductors)

TL;DR

Principal Collateral Device Engineer (Semiconductors): Developing next-generation device and interconnect technology to ensure world-class process device performance with an accent on CMOS semiconductor device physics and test chip design. Focus on defining derivative architectures, optimizing design rules for advanced nodes, and bridging the gap between process integration and design.

Location: Hybrid; must be based in the US (Santa Clara, CA; Phoenix, AZ; or Hillsboro, OR)

Salary: $224,970 - $317,600 USD

Company

hirify.global is transforming into a leading foundry service provider, offering world-class semiconductor manufacturing capabilities to customers worldwide.

What you will do

• Lead cross-functional groups in defining derivative architectures, including design rules, transistors, and interconnects.
• Design test chips and develop scribe line layout and process monitoring structures.
• Develop, validate, and manage design rules and waiver processes.
• Act as a key interface between Process Integration, Yield, Device, and Design teams utilizing DTCO skills for SRAM and Standard cells.
• Utilize data analysis, scripting, and statistical techniques for test chip data interpretation.
• Apply Design of Experiment (DOE) principles to optimize device collateral solutions.

Requirements

• Master's or Ph.D. degree in Electrical Engineering, Physics, or a related field.
• 15+ years of experience in CMOS device engineering, focusing on test chip design and collateral development.
• Expertise in CMOS semiconductor device physics and advanced transistor device architecture.
• Proficiency in design rule checker (DRC) development and physical verification flows.
• Experience in high-volume manufacturing (HVM) environments with a focus on yield monitoring and process control.

Nice to have

• Hands-on experience with advanced node test chip design (3nm-16nm FinFETs and sub-3nm GAA FETs).
• Knowledge of mask generation, including Boolean/OPC.
• Advanced knowledge of statistical process control (SPC) and data analytics.

Culture & Benefits

• Hybrid work model allowing a split between on-site and off-site work.
• Competitive total compensation package including stock bonuses.
• Comprehensive benefit programs covering health, retirement, and vacation.
• Opportunity to contribute to state-of-the-art semiconductor manufacturing for the AI era.