CPU–SoC Mask Layout Designer (Silicon Engineering)

TL;DR

CPU–SoC Mask Layout Designer (Silicon Engineering): Creating mask layouts of integrated circuits and running design verification tools for next-generation SOC/CPU with an accent on reliability checks and physical design. Focus on designing floorplans, power grids, and resolving issues related to EM, IR, and ESD.

Location: Hybrid in Penang or Kulim, Malaysia

Company

hirify.global is a global leader in semiconductor innovation, focusing on the design and development of advanced CPU and SoC technologies.

What you will do

• Create mask layouts of integrated circuits based on provided specifications.
• Execute design verification tools for process design rules, electron migration (EM), voltage drop (IR), and ESD.
• Design and analyze floorplans, power grids, and bumps.
• Collaborate with internal and external stakeholders to align on project goals and resolve technical issues.
• Troubleshoot layout issues and optimize the layout design flow and methodology.

Requirements

• Diploma in Electrical and Electronic Engineering or related fields.
• Fresh graduate status.
• Must be willing to work in Penang or Kulim, Malaysia.
• Proficiency in English.
• Open to a contract-based employment relationship.

Nice to have

• Familiarity with Unix.
• Knowledge of VLSI, SoC/CPU Architecture, or System Verilog.

Culture & Benefits

• Hands-on exposure to cutting-edge silicon design.
• Mentorship from experienced industry experts.
• World-class engineering environment with global collaboration.
• Continuous learning and professional development opportunities.
• Hybrid work model allowing a split between on-site and off-site work.