Physical Design Engineer (ASIC/SoC)

TL;DR

Physical Design Engineer (ASIC/SoC): Transforming designs from RTL to GDS to create manufacturing-ready databases for high-performance silicon solutions with an accent on power, frequency, and area optimization. Focus on executing end-to-end physical design implementation, clock tree synthesis, and timing closure for custom IP and SoC.

Location: On-site in Penang, Malaysia

Company

hirify.global's Central Engineering Group (CEG) is a data-driven organization building scalable engineering solutions across product enablement, custom ASIC, and foundry enablement.

What you will do

• Perform end-to-end physical design implementation of custom IP and SoC designs from RTL to GDS.
• Conduct floor planning, power and clock distribution, and clock tree synthesis to optimize performance.
• Execute place and route tasks, ensuring accurate pin/macro placement and robust layout cleanup.
• Drive static timing analysis, power noise analysis, and reliability verification to achieve timing closure.
• Lead design verification and signoff processes, including formal equivalence and electrical rule checking.
• Improve physical design methodologies and automate flows using Perl, TCL, or Unix shell scripting.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience (Bachelor's) or 2+ years (Master's) in the structural and physical design domain.
• Proficiency with RTL to GDS flows and industry-standard EDA tools for physical design and verification.
• Expertise in clock design, clock tree synthesis, timing closure, and multi-power domain analysis.
• Strong knowledge of digital design principles, CMOS processes, and low-power design techniques.
• Must be based in or able to work on-site in Penang, Malaysia.

Nice to have

• Postgraduate degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with standard-cell-based VLSI design methodology and advanced EDA tools.
• Ability to lead technical development within a physical design team and mentor junior engineers.
• Track record of resolving complex design challenges in ASIC/SoC convergence.

Culture & Benefits

• Opportunity to play a pivotal role in shaping the future of custom IP and SoC designs.
• Work in a high-impact environment delivering scalable, energy-efficient silicon solutions.
• Collaborative, multidisciplinary team environment focused on semiconductor innovation.
• Commitment to ethical hiring practices and Responsible Business Alliance (RBA) compliance.