Integrated Circuit Design Verification Engineer (ASIC)

TL;DR

Integrated Circuit Design Verification Engineer (ASIC): Developing and implementing advanced verification methodologies for display Integrated Circuits in AR hardware with an accent on UVM-based testbenches and functional coverage. Focus on creating robust verification plans, automating test flows, and ensuring high-quality RTL design for next-generation Spectacles.

Location: Must be based in the US and work onsite 4+ days per week

Company

Snap Inc. is a technology company focused on enhancing human communication and expression through visual messaging and augmented reality hardware.

What you will do

• Design display Integrated Circuits for AR applications as part of a multi-disciplinary team.
• Develop and implement UVM-based and assertion-based testbenches.
• Create and execute comprehensive verification test plans, including functional and code coverage.
• Utilize Siemens Questa for verification and debug tasks.
• Configure tools and create automation scripts using Python, Perl, and TCL.
• Collaborate with digital design, analog logic, and software engineering teams.

Requirements

• 10+ years of experience in ASIC Design Verification.
• Strong knowledge of UVM and SystemVerilog.
• Proficiency in digital functional simulation and Siemens Questa tools.
• Experience with Verilog RTL coding practices.
• Scripting and automation skills in a Linux environment.
• Excellent written and verbal English communication skills.

Nice to have

• Experience with the entire verification process from planning to sign-off.
• Background in emulation and RTL design.
• Familiarity with video and display systems, MIPI, AMBA, I2C, SPI, and embedded microcontrollers.
• Knowledge of ASIC test or production flow.

Culture & Benefits

• Comprehensive medical coverage and emotional/mental health support.
• Paid parental leave.
• Compensation packages including long-term success sharing.
• Collaborative "Default Together" office culture.