Назад
Company hidden
4 часа назад

ASIC Design Verification Engineer (Space)

130 000 - 200 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
middle/senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

ASIC Design Verification Engineer (Space): Verifying the functionality, performance, and robustness of custom silicon designs for high-power satellite platforms with an accent on SystemVerilog/UVM testbench development and coverage closure. Focus on driving constrained-random testing strategies, managing simulation environments, and collaborating across architecture and RTL teams to ensure first-generation silicon success.

Location: Must be based in Seattle, WA (Onsite)

Salary: $130,000 – $200,000

Company

A Series C space startup building the largest and highest-power satellite platforms for missions from LEO to deep space.

What you will do

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches including agents, monitors, scoreboards, and coverage models.
  • Implement SystemVerilog Assertions (SVA) and integrate formal verification.
  • Drive constrained-random and directed testing to validate functionality and stress scenarios.
  • Run simulations, triage failures, and collaborate with RTL designers on root-cause analysis.
  • Manage regression testing, simulation farms, and CI pipelines for fast debug iterations.

Requirements

  • Must be a U.S. Person (citizen, permanent resident, or protected individual) due to ITAR regulations.
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with simulation tools (VCS, Xcelium, Questa) and waveform debug (Verdi, SimVision).
  • Experience with test planning, testbench development, and coverage analysis.

Nice to have

  • Experience with UVM-based testbench development and regression management.
  • Familiarity with developing and integrating reference models.
  • Understanding of RTL design flows and industry standard interfaces (APB/AHB/AXI).
  • Experience in space, telecom, or RF/digital mixed systems.

Culture & Benefits

  • Equity in the company.
  • Comprehensive medical, dental, and vision coverage.
  • Paid time off and paid parental leave.
  • Life insurance and other perks.
  • Fast-paced, high-ownership environment in a groundbreaking space startup.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →