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3 дня назад

IP Release Principal Engineer (Semiconductor)

158 600 - 237 600$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

IP Release Principal Engineer (Semiconductor): Serving as the quality gatekeeper for IP subsystem deliveries within the Custom Compute and Storage business unit with an accent on RTL static analysis, synthesis readiness, and DFT enablement. Focus on driving the complete front-end release qualification flow, triaging integration issues, and ensuring all IP packages meet stringent quality and methodology standards for SoC integrators.

Location: Must be based in Santa Clara, CA

Salary: $158,600–$237,600 per annum

Company

hirify.global is a leading semiconductor company providing essential data infrastructure solutions across enterprise, cloud, and AI architectures.

What you will do

  • Own the full RTL static analysis sign-off flow including Lint, CDC, and RDC checks.
  • Drive front-end synthesis readiness, validating timing constraints, SDC, and UPF.
  • Ensure DFT considerations are integrated into IP subsystems, including scan insertion and BIST hooks.
  • Execute the IP delivery checklist at each milestone to verify collateral completeness.
  • Act as the primary technical point of contact for SoC integration teams to triage and resolve integration issues.
  • Collaborate with cross-functional teams to align on methodology and contribute to AI automation for release flows.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field.
  • 10-15 years of professional experience (or 5-10 years with advanced degree).
  • Must be eligible to access export-controlled information under U.S. law.
  • Extensive experience in Verilog and static quality checks of implemented RTL.
  • Proven track record in large design synthesis, floor planning, and timing closure.
  • Hands-on experience with interpretive languages such as Python or Perl.

Nice to have

  • Domain expertise in SoC architecture, processor cores, memory, PCIe, or CXL.
  • Experience with leading foundries and advanced process nodes (2nm, 3nm, 5nm).
  • Experience with memory generation.

Culture & Benefits

  • Comprehensive financial well-being programs including an employee stock purchase plan.
  • Robust mental health resources and family support programs.
  • Recognition and service awards for contributions and milestones.
  • Commitment to purposeful innovation and professional growth.

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