Lead Design Engineer (Layout)

TL;DR

Lead Design Engineer (Layout): Developing custom layout floorplans and mixed-signal routing for high-speed PHYs with an accent on noise reduction and top-level hierarchy. Focus on executing DRC/LVS/ERC and EMIR analysis to ensure high-efficiency analog layout design.

Location: Shanghai

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools for the semiconductor and electronics industries.

What you will do

• Develop custom layout floorplans, matching guides, and resistor/capacitor placement.
• Implement sensitive and mixed-signal routing while minimizing coupling and noise.
• Create top-level hierarchy floorplans for blocks and power distribution.
• Design high-speed mixed-signal PHYs, including SerDes, USB, and DDR.
• Collaborate with analog circuit design teams to ensure high layout quality and efficiency.

Requirements

• BSEE degree with 5+ years of experience in analog/custom layout for advanced technology nodes.
• Proficiency with layout edit/verify tools such as Virtuoso XL and Pegasus/Calibre (DRC/LVS).
• Expertise in EMIR tools, specifically Voltus-FI.
• Hands-on experience conducting DRC/LVS/ERC and EMIR analysis and implementing appropriate solutions.
• Strong fundamental understanding of IC design technology and process methodology.
• Good communication skills in English.

Nice to have

• Work experience with PERC runs.
• Experience in FinFET layout.
• Knowledge of ESD/Latch-up.
• Experience collaborating with digital P&R teams.