Senior/Staff Frontend Engineer (SoC)

TL;DR

Senior/Staff Frontend Engineer (SoC): Developing Verilog RTL for RISC-V based CPU architectures and ensuring verification closure with an accent on functional coverage and debugging. Focus on implementing high-quality processor IP and collaborating across pre-silicon and post-silicon stages.

Location: Singapore / Malaysia

Company

hirify.global is a world-leading technology company for Bitcoin mining and AI cloud, specializing in ASIC chips and high-performance computing datacenters.

What you will do

• Implement Verilog RTL for CPUs/processors, specifically focusing on RISC-V architectures.
• Ensure 100% functional coverage to support and achieve verification closure.
• Contribute to design verification and debug issues across pre-silicon and post-silicon stages.
• Collaborate with software development teams to deliver high-quality processor IP.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 5+ years of experience in semiconductor or high technology R&D.
• Proven experience in Verilog RTL development within an SoC/IP environment.
• Strong understanding of CPU/processor architecture and logic design.
• Proficiency in scripting languages such as Perl, Shell, or TCL to automate design tasks.

Culture & Benefits

• Inclusive environment with open workspaces and a dynamic start-up spirit.
• Direct opportunity to make a significant impact on the digital asset industry.
• High degree of personal accountability, autonomy, and opportunities for fast professional growth.
• Attractive welfare benefits, including training and mentoring programs.