Staff SoC RTL Engineer (AI)

TL;DR

Staff SoC RTL Engineer (AI): Designing and optimizing high-performance chiplet-based SoC architectures with an accent on RTL implementation, microarchitecture, and PPA optimization. Focus on building custom IP blocks, interconnect designs, and integrating RISC-V architectures for AI platforms.

Location: Hybrid, based in Tokyo, Japan

Company

hirify.global is leading the industry in cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms.

What you will do

• Define, build, and optimize high-performance chiplet-based SoC architectures.
• Implement RTL for custom IP blocks and SoC components using HDLs.
• Optimize designs for power, performance, and area (PPA) under aggressive goals.
• Collaborate on specification definitions, peer reviews, and team-wide planning.
• Support backend teams with synthesis and timing closure awareness.
• Contribute to validation using emulation, FPGA prototyping, or UVM flows.

Requirements

• Expertise in digital design, computer architecture, and IP microarchitecture.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Experience with full ASIC flows and timing closure.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).
• Location: Must be based in Tokyo, Japan (Hybrid).

Nice to have

• Prior experience in on-chip fabric and interconnect designs.
• Basic understanding of RISC-V Architecture and debug experience.

Culture & Benefits

• Highly competitive compensation package and benefits.
• Opportunity to work on cutting-edge chiplet design from spec to silicon.
• Collaboration with teams designing novel processor and memory architectures.
• Cross-functional environment involving design, DV, physical, and firmware teams.