Sr Staff Engineer, SoC RTL Design (AI)

TL;DR

Sr Staff Engineer, SoC RTL Design (AI): Defining and optimizing high-performance IP and SoC architectures for next-generation AI and compute workloads with an accent on microarchitecture and RTL implementation. Focus on optimizing power, performance, and area (PPA) to build cutting-edge AI hardware.

Location: Hybrid (Toronto, Ottawa, Boston, or Austin)

Company

hirify.global is leading the industry in AI technology by developing high-performance RISC-V CPUs and AI platforms to redefine the computing paradigm.

What you will do

• Implement architecture and RTL for custom IP blocks and SoC components.
• Design compute, interconnect, or memory-heavy blocks with a focus on performance.
• Contribute to hardware validation using emulation, FPGA prototyping, or UVM flows.
• Support backend teams through synthesis and timing closure awareness.
• Collaborate across design, DV, physical, and firmware teams to bring chips from spec to silicon.

Requirements

• Deep expertise in computer architecture and IP microarchitecture.
• Proficiency in RTL development using Verilog or VHDL.
• Experience with full ASIC flows and PPA optimization.
• Must be eligible to access U.S. export-controlled technology (compliance with EAR laws).
• Must be based in or able to work from Toronto, Ottawa, Boston, or Austin.

Culture & Benefits

• Competitive compensation package and benefits.
• Collaborative environment with a passion for solving hard technical problems.
• Opportunity to work on novel processor and memory architectures.
• Equal opportunity employer.