Senior Logic Design Verification Engineer

TL;DR

Senior Logic Design Verification Engineer (Embedded/SoC): Developing and verifying Power Management Controller IP for client and server chipsets with an accent on UVM-based testbench architecture and RTL validation. Focus on building complex test environments, debugging system-level hardware-firmware interactions, and ensuring the functionality of next-generation silicon designs.

Location: Must be based in Penang, Malaysia (Hybrid work model available).

Company

hirify.global is a global leader in silicon and platform engineering, delivering breakthrough computing solutions for the next generation of technology.

What you will do

• Collaborate with IP architects to define and develop verification testbenches and RTL models.
• Validate new architectural features by creating comprehensive test plans, content, and tools.
• Implement corrective measures for failing RTL tests and analyze results to refine testing strategies.
• Debug and resolve complex issues on system platforms using software and RTL simulation tools.
• Influence cross-organizational boundaries by working closely with manufacturing and validation partners.

Requirements

• Bachelor's, Master's, or Ph.D. in Electronics or Computer Engineering.
• At least 15 years of relevant experience in design verification.
• Expertise in UVM and SystemVerilog, including building testbenches from the ground up.
• Strong analytical and debugging skills with experience in Linux and scripting languages like Python or Perl.
• Knowledge of hardware-firmware co-validation, ACPI specifications, and power management.
• Ability to work independently and communicate effectively within a team environment.

Culture & Benefits

• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on industry-leading silicon and platform technologies.
• Commitment to ethical hiring practices and RBA compliance.
• Collaborative environment focused on innovation and technical excellence.