Principal DFT Engineer (SoC/ASIC)

TL;DR

Principal DFT Engineer (SoC/ASIC): Implementing and verifying DFT solutions for complex hierarchical SoC and ASIC designs with an accent on scan insertion, ATPG generation, and silicon bring-up. Focus on ensuring first-pass silicon success through rigorous DFT verification, collaboration with physical design and ATE teams, and optimizing test strategies for high-quality production.

Location: Taipei, Taiwan (Neihu-Ruiguang Road)

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Develop and implement DFT architectures for hierarchical SoC and ASIC designs.
• Perform scan insertion, test point insertion, and test compression using industry-standard architectures.
• Validate Serial Stream Network (SSN) topology and manage scan chain balancing.
• Generate and analyze ATPG patterns to ensure optimal test coverage for stuck-at, transition, and path delay faults.
• Perform comprehensive DFT verification using Verilog and gate-level simulations.
• Collaborate with ATE engineers to validate timing and pattern files for production readiness.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 3 years of experience in DFT design and verification (5+ years preferred).
• Strong understanding of scan-based test architectures and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level verification.
• Strong scripting skills in TCL, Perl, or Python for automation.

Culture & Benefits

• Opportunity to work at a global semiconductor industry leader.
• Engagement with complex, high-scale SoC/ASIC projects.
• Collaboration with cross-functional teams including physical design and ATE test experts.
• Access to extensive internal resources and professional development materials.