ASIC Design Engineer (AI)

TL;DR

ASIC Design Engineer (AI): Developing advanced ethernet protocols and high-performance SoCs for AI and HPC networking with an accent on micro-architecture specification and timing closure. Focus on pre-silicon design verification and post-silicon system-level debugging to ensure optimal performance in large-scale compute clusters.

Location: Must be based in Costa Rica (Remote via EOR).

Company

hirify.global delivers high-performance scale-out networking solutions for AI and HPC datacenters, integrating hardware and software to maximize compute cluster efficiency.

What you will do

• Implement advanced ethernet protocols for next-generation ASICs.
• Author detailed micro-architecture specifications.
• Define timing constraints for RTL blocks and collaborate on timing optimization.
• Create block and system-level test plans in coordination with verification teams.
• Resolve complex ASIC issues through post-silicon hardware and firmware debugging.

Requirements

• Must be based in Costa Rica.
• B.S. or M.S. in Computer or Electrical Engineering.
• 3+ years of professional experience in digital design.
• Proficiency in Verilog and System Verilog.
• Experience with timing closure and physical design methodologies.
• Strong system-level debugging and root cause analysis skills.

Nice to have

• Experience with Ethernet architecture and networking protocols.
• Familiarity with ethernet adapters and switches design.
• Experience with multiple clock designs and asynchronous interfaces.

Culture & Benefits

• Competitive compensation package including base salary and performance incentives.
• Equity participation opportunities.
• Flexible work arrangements.
• Global organization with a collaborative, forward-thinking team.