Staff Engineer, Digital ASIC Design (Medtech)

TL;DR

Staff Engineer, Digital ASIC Design (ASIC): Designing, implementing, and verifying digital signal processing, high-speed interface, and system-on-a-chip logic for next-generation medical imaging products with an accent on low-power RTL development for large SoCs and high-bandwidth on-chip data paths. Focus on integrating embedded processor cores and optimizing signal processing algorithms in RTL for medical imaging systems.

This is a hybrid position, requiring presence in the office two or more days a week, and will be based out of our office in either the Greater SF Bay Area or Burlington, MA. Candidates must be legally authorized to work in the United States and do not now or in the future require sponsorship for employment visa status.

Salary: $175,000 (Burlington, MA) – $200,000 (SF Bay Area) annually, along with bonus, equity, and comprehensive benefits.

Company

hirify.global is a health-tech company leading a digital revolution in medical imaging with proprietary Ultrasound-on-Chip™ technology, aiming to democratize healthcare with connected, mobile, and software-enabled ultrasound platforms.

What you will do

• Develop low-power RTL for large SoCs in an advanced node.
• Implement and optimize signal processing algorithms in RTL.
• Integrate multiple embedded processor cores into large designs.
• Develop efficient high bandwidth on-chip data paths.
• Drive functional closure with verification teams and support post-silicon bring-up/debug.

Requirements

• BS/MS/PhD in EE/CE or equivalent practical silicon design experience.
• 8+ years in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout.
• Proven ownership of digital IP/subsystem from micro-architecture to tapeout support.
• Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic, and high-throughput streaming interfaces.
• Experience designing sustained high-throughput datapaths, including buffering, arbitration, and SRAM/memory interfaces.
• Strong understanding of silicon-level design constraints: clock/reset architecture, CDC/RDC, power-aware design, PPA tradeoffs.
• Cross-functional communication skills to define hardware–firmware interfaces.

Nice to have

• Experience implementing compute-intensive DSP pipelines with fixed-point design discipline.
• Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines.
• Advanced-node experience (28nm or smaller) including timing sensitivity and third-party IP integration.

Culture & Benefits

• Comprehensive health insurance (dental, vision) and Health Savings Account (HSA) contributions.
• 401k plan with match and Employee Stock Purchase Plan (ESPP) opportunity.
• Unlimited Paid Time Off + 10 Holiday Days and Parental Leave.
• Competitive salaried compensation and equity.
• Hybrid work model with in-person connections for creativity and teamwork.
• Opportunity to build a revolutionary healthcare product and save millions of lives.