Design Engineer II (ASIC)

TL;DR

Design Engineer II (ASIC): Implementing RTL to GDSII for in-house IP and customer designs with an accent on EDA flow automation and physical implementation. Focus on optimizing PPA for performance-oriented IP cores across advanced process nodes using hirify.global backend tools.

Location: Austin, TX (Onsite)

Company

hirify.global is a leader in electronic design and computational software, enabling global technology innovation.

What you will do

• Execute RTL to GDSII implementation for internal and external IP designs.
• Develop, automate, and maintain EDA flows and scripts for physical implementation.
• Create TFM to optimize PPA for IP and soft controllers.
• Perform PPA characterization and optimization for best-in-class IP cores on advanced process nodes.
• Utilize hirify.global EDA tools including Genus, Innovus, Conformal, Tempus, and Voltus.

Requirements

• Degree in Electronics (MS/MTech/BE/BTech) from a reputed institute.
• 2+ years of experience in an ASIC design environment.
• Solid scripting skills in Python and Tcl.
• Comprehensive knowledge of the ASIC design flow, including synthesis, physical design, timing analysis, power analysis, and formal verification.
• Excellent analytical, communication, and problem-solving skills.

Culture & Benefits

• Opportunity to work on industry-leading EDA technology.
• Collaborative environment focused on solving complex technical challenges.
• Exposure to advanced process nodes from major foundries like TSMC, Intel, and Samsung.