Senior Physical Design Engineer (Core IP)

TL;DR

Senior Physical Design Engineer (Core IP): Designing and optimizing high-speed CPU core IP for client, server, and AI processors with an accent on synthesis, place and route, and design closure. Focus on developing reproducible design convergence strategies, refining synthesis flows, and ensuring performance requirements are met on advanced process technologies.

Location: On-site in Hillsboro, Oregon, USA

Salary: $164,470–$269,100 USD

Company

hirify.global is a global leader in semiconductor innovation, creating processors and technologies that power the cloud, IoT, and 5G connectivity.

What you will do

• Perform logic synthesis, place and route, and design closure for high-speed CPU cores.
• Execute design flow tasks including FEV, power analysis, timing analysis, and quality checks.
• Develop and refine synthesis strategies to deliver reproducible design convergence.
• Recommend and implement best practices for design methodology and synthesis flows.
• Collaborate with clocking and full-chip teams to balance timing, power, and partitioning.

Requirements

• Must be eligible to work in the US without hirify.global immigration sponsorship.
• On-site presence required in Hillsboro, Oregon.
• Bachelor's degree with 10+ years or Master's degree with 5+ years of relevant experience.
• Expertise in integrated circuit design tools like Synopsys or Cadence.
• Proficiency in scripting with TCL and at least one other language (Python, Perl, or Ruby).
• Proven success in digital logic block synthesis integrated into large SoC or IP.

Culture & Benefits

• Competitive total compensation package including pay and stock bonuses.
• Comprehensive health and retirement benefit programs.
• Paid vacation and time-off policies.
• Opportunity to work on cutting-edge microprocessor architecture.
• Collaborative environment focused on solving complex technical challenges.