Staff Digital Design Engineer

TL;DR

Staff Digital Design Engineer (ASIC Digital Design): Architecting and implementing digital IP blocks and subsystems for neuromorphic SoCs with an accent on RTL-level microarchitecture, verification collaboration, and PPA-focused low-power design. Focus on translating high-level requirements into RTL specifications, driving synthesis/STA and timing constraints, integrating third-party IP, and supporting tapeout while mentoring engineers and shaping internal design methods.

Company

hirify.global develops ultra-efficient neuromorphic processors for AI at the edge.

What you will do

• Architect, design, and implement digital IP blocks and subsystems for neuromorphic SoCs.
• Translate high-level product and algorithmic requirements into RTL-level specifications and microarchitectures.
• Own front-end digital design activities: RTL coding (SystemVerilog/Verilog), simulation, synthesis, STA, and design documentation.
• Collaborate with verification on test plans and co-develop functional testbenches.
• Draft timing constraints and work with backend engineers during physical design and gate-level simulation.
• Integrate third-party IP, optimize for PPA using low-power techniques, and mentor junior engineers through code reviews and design-method improvements.

Requirements

• 7+ years of hands-on ASIC digital design experience, including complex IP blocks and SoC-level integration.
• Strong RTL design and debugging skills in SystemVerilog/Verilog.
• Deep understanding of SoC architecture, memory-mapped bus interfaces, and IP integration flows.
• Experience with Cadence tools and EDA flows, including synthesis and static timing analysis.
• Familiarity with DFT, gate-level simulations, and low-power design methodologies.
• Experience drafting specifications/design documents and exposure to functional verification and testbench writing or review.

Culture & Benefits

• Flexible working environment with work-from-home policy and flexible working hours.
• Inclusive culture with support for holistic and personal development.
• Ambitious teams with freedom to innovate in a strong engineering culture.
• Advantageous holidays scheme.

Hiring process

• Application review followed by interviews to assess technical fit and collaboration approach.
• Discussion of experience across RTL design, verification, timing/physical design, and SoC integration.

Location: Rijswijk Office; Ireland (Remote); United Kingdom (Remote)