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2 дня назад

Senior Staff Engineer, Digital IC Design

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff Engineer, Digital IC Design (ASIC/SerDes): Developing post-RTL digital IC implementations for high-speed SerDes PHY and analog mixed-signal IPs with an accent on synthesis, timing closure, DFT, and physical design. Focus on closing block- and chip-level timing, performing custom placement and routing for mixed-signal designs, and supporting silicon delivery across multiple product lines.

Location: Hsinchu, Taiwan; onsite, full-time.

Company

hirify.global develops semiconductor solutions and infrastructure technologies for enterprise, cloud, AI, and carrier applications.

What you will do

  • Perform block- and chip-level synthesis, timing closure, DFT generation, and engineering change orders.
  • Support synthesis, timing analysis, and physical implementation for SerDes IPs operating from 10Gbps to 224Gbps.
  • Improve digital design methodologies and post-RTL implementation flows.
  • Collaborate with analog and digital design teams to deliver SerDes and analog mixed-signal IP solutions.
  • Provide pre-silicon and post-silicon support to product teams.

Requirements

  • Master’s degree or PhD in electrical engineering, computer science, or a related field, with 6+ years of experience.
  • Strong post-RTL experience in synthesis, timing analysis, physical design, and block- and top-level physical timing closure.
  • Experience with custom placement and routing for mixed-signal designs and flexibility across post-RTL activities.
  • Proficiency with logic or physical synthesis using Synopsys or Cadence tools.
  • Experience with DFT generation and verification, Static Timing Analysis using PrimeTime, and physical design for 28nm and beyond.
  • Strong Perl and Tcl scripting skills, plus effective communication and teamwork.

Nice to have

  • Low-power design and circuit-level or custom design experience.
  • Floorplanning, clock-tree synthesis, power planning and analysis, signal integrity, or physical verification experience.

Culture & Benefits

  • Competitive compensation and benefits.
  • Collaborative, transparent, and inclusive work environment.
  • Resources and development opportunities to support professional growth.
  • Interview participants may not use AI tools or automated recording and assistance tools without prior interviewer approval.
  • Access to export-controlled technology may require eligibility under U.S. export control laws and, for some applicants, an export license review.

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