Physical Design Engineer II (PNR/Physical Verification/STA/EMIR)

TL;DR

Physical Design Engineer II (PNR/Physical Verification/STA/EMIR): Participating in and leading next-generation physical design, methodology, and flow development for advanced technology nodes with an accent on PNR implementation, timing closure, and physical verification signoff. Focus on solving complex DRC/LVS/antenna and EM/IR issues to ensure successful tapeouts.

Location: Toronto 02

Company

hirify.global develops technology solutions for semiconductor design and verification.

What you will do

• Participate in or lead next-generation physical design, methodology, and flow development in advanced technology nodes.
• Implement physical design: floor planning, power grid design, place and route, clock tree synthesis, and timing closure.
• Drive signoff activities including power/signal integrity, physical verification (DRC/LVS/Antenna), and EM/IR signoff.
• Support DFM closure and fix physical design violations across DRC/DFM/LVS/ANT/ERC.
• Work closely with RTL design and analog teams to ensure successful tapeouts.

Requirements

• Bachelor’s degree or above in EE/CS/IT with 3+ years of work experience.
• Extensive knowledge of design rules for N7/N5 and below.
• Strong static timing analysis experience.
• Knowledge of scripting languages and their use in methodology.
• Ability to fix physical design violations including DRC, DFM, LVS, ANT, and ERC.
• Strong communication and teamwork skills.

Culture & Benefits

• Opportunity to work on challenging low-power and high-speed designs.
• Collaboration with RTL and analog teams to support tapeouts.
• Inclusive hiring with support for accessibility needs during the application and interview process.