R&D Physical Design Engineer

TL;DR

R&D Physical Design Engineer (ASIC/VLSI): Implement physical design for ASICs, covering floor planning, placement, design closure, STA, and DRC/LVS with an accent on full-chip signoff workflows and tapeout readiness. Focus on independently handling block implementation/top-level tasks and solving complex VLSI design challenges across advanced nodes like 7nm.

Location: China (Shanghai, Zhangjiang Hi Tech)

Company

hirify.global is an equal opportunity employer.

What you will do

• Implement physical design including floor planning, placement, and design closure.
• Run and support STA and DRC/LVS to ensure design correctness and timing closure.
• Handle block implementation and top-level physical design tasks independently.
• Support full-chip signoff activities such as PI, SI, PV, and STA.
• Contribute to tapeout execution for advanced process nodes.

Requirements

• Strong background in physical design (floor planning, placement, design closure, STA, DRC/LVS).
• Good understanding of ASIC design flow and solid VLSI background.
• Ability to execute block implementation/top-level tasks independently.
• Tapeout experience in 7nm and advanced process design.
• Strong communication and problem-solving skills.
• Good scripting skills in Perl/Tcl.

Nice to have

• Experience with DFT insertion.
• Experience with Power/IVD analysis.
• Experience with STA.

Culture & Benefits

• Equal opportunity employment.
• Consideration of qualified applicants regardless of protected characteristics.
• Application guidance for candidates located outside the USA to provide a home address for correspondence.