STA Engineer (ASIC)

TL;DR

STA Engineer (ASIC): Managing timing closure for high-performance, power-efficient ASICs with an accent on sub-micron technology constraints and multi-scenario timing analysis. Focus on implementing timing infrastructure, creating timing ECOs, and optimizing complex SoC designs through deep path analysis and scripting.

Location: Must be based in Fort Collins, Colorado, USA

Salary: $129,400 - $207,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Collaborate with design teams to debug constraints and facilitate logic changes for improved timing.
• Work closely with Physical and Logic Design teams to identify and resolve timing issues.
• Create and implement timing ECOs for project tapeouts.
• Develop and maintain scripts and methodologies for timing analysis and execution.
• Perform deep analysis of timing paths to identify and mitigate key performance bottlenecks.
• Implement and manage robust timing infrastructure.

Requirements

• MSEE or equivalent degree required.
• 10+ years of relevant industry experience.
• 5-10 years of hands-on experience in Static Timing Analysis (STA).
• Proficiency in timing flows using industry-standard tools and deep understanding of noise, cross-talk, and OCV effects.
• Strong programming skills in Perl and TCL.
• Familiarity with circuit modeling, including SPICE models and worst-case corner selection.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and equity award opportunities.
• Paid holidays, sick leave, and vacation time.
• Support for Paid Family Leave and other applicable leaves of absence.