Senior Principal Embedded Firmware Software Engineer (Networking)

TL;DR

Senior Principal Embedded Firmware Software Engineer (Networking): Leading the architecture, design, and development of embedded C firmware for high-performance DSP products used in data centers and AI clusters with an accent on signal processing, FEC, and RISC-V MCU control. Focus on translating complex industry standards into technical requirements and solving critical hardware-software integration challenges.

Location: Santa Clara, CA

Salary: $154,680 - $231,700 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across cloud, enterprise, and AI architectures.

What you will do

• Lead the architecture, design, and testing of embedded C firmware for complex DSP hardware.
• Guide software team members (2-8 developers) through the full development lifecycle from pre-silicon simulation to field deployment.
• Develop firmware for DSP control blocks, including RX/TX signal processing, FEC, PLL/FLL, and thermal monitoring.
• Coordinate with cross-functional teams (Marketing, Hardware, QA) to align on deliverables and milestones.
• Lead technical discussions with tier-1 customers regarding feature requirements and API specifications.
• Mentor engineers on debugging techniques and best practices for embedded firmware development.

Requirements

• Experience in memory-constrained embedded C/C++ firmware development.
• Proven experience as a Software Team Lead or Technical Lead on embedded projects.
• Strong understanding of embedded SoC, MCU architecture (RISC-V preferred), and memory-mapped interfaces.
• Must be eligible to access export-controlled information (EAR).
• Excellent verbal and written communication skills in English.
• Proficiency in solving complex debug issues on real hardware in a lab environment.

Nice to have

• Experience with SERDES, IM-DD/Coherent DSP, or Ethernet/PCIe PHYs.
• Familiarity with RTOS, Linux kernel, or bare-metal development.
• Proficiency in Python and experience with git, gdb, and makefiles.
• Knowledge of digital verification, FPGA emulation, or Verilog.
• Understanding of the OSI model and PHY layer traffic schemes.

Culture & Benefits

• Comprehensive financial well-being programs, including an employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for contributions and milestones.

Hiring process

• Interviews focused on evaluating individual experience, thought process, and communication skills in real time.
• Use of AI tools (ChatGPT, Copilot, etc.) during interviews is strictly prohibited and will result in disqualification.