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2 дня назад

Senior Staff RTL Design Engineer (SoC)

135 900 - 201 130$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff RTL Design Engineer (SoC): Designing and integrating complex IP for high-performance SoC/ASIC products used in AI infrastructure and cloud computing with an accent on microarchitecture, RTL development, and PPA optimization. Focus on implementing interconnects, memory interfaces, and resolving subsystem-level issues for advanced process nodes.

Location: Onsite in Boise, ID

Salary: $135,900 - $201,130 per annum

Company

hirify.global provides semiconductor solutions that serve as the essential building blocks of data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

  • Define microarchitecture and develop Verilog/SystemVerilog RTL for SoC-level components, including interconnects and memory interfaces.
  • Implement and integrate complex IP across subsystems to meet performance, power, and area (PPA) targets.
  • Collaborate with verification teams to review test plans, support functional debug, and close coverage gaps.
  • Execute design checks (lint, CDC/RDC), define timing constraints, and collaborate with physical design teams for implementation.
  • Coordinate with IP teams to integrate complex interfaces and resolve subsystem-level technical issues.
  • Contribute to design methodology and provide technical guidance to other engineers.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Science, or related field with 8-12 years of experience, or Master's/PhD with 5-10 years.
  • Deep experience in micro-architecture for complex Custom SoC/ASIC products.
  • Proficiency in RTL design, synthesis, static-timing closure, and formal verification.
  • Hands-on experience with front-end design tools and chip-development processes.
  • Knowledge of scripting languages, specifically Python.
  • Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Nice to have

  • Design knowledge of industry-standard bus protocols such as AXI, AHB, or APB.
  • Experience with high-speed, low-power, and area-optimized designs.
  • Experience with multi-clock designs, DFT, resets, LEC, and Lint.

Culture & Benefits

  • Employee stock purchase plan with a 2-year look back.
  • Comprehensive family support programs to help balance professional and personal life.
  • Robust mental and physical health resources.
  • Recognition and service awards for career milestones and contributions.

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