Principal Design Engineer (Virtual Solution)

TL;DR

Principal Design Engineer (Virtual Solution) (Emulation/SoC): Designing and developing system-level AVIP solutions for emulation and prototyping platforms with an accent on high-speed protocols and SoC validation. Focus on architecting scalable verification flows, optimizing emulation efficiency, and integrating AI/ML-based verification methodologies.

Location: Shanghai

Company

hirify.global is a global leader in electronic systems design and software tools for the semiconductor and electronics industries.

What you will do

• Design and develop system-level AVIP solutions for Palladium and Protium emulation/prototyping platforms.
• Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation.
• Develop end-to-end verification flows, including testbench and system modeling.
• Architect scalable solutions for multi-protocol system validation across multiple clock domains.
• Create custom test cases and automation tools for embedded and hybrid flows.
• Collaborate with global cross-functional teams and customers to debug and resolve system-level issues.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5-10 years of professional experience in design or verification.
• Expertise in high-speed protocols such as PCIe, CXL, AMBA, UCIe, or Ethernet.
• Strong RTL design skills using SystemVerilog/Verilog and C/C++ development for system integration.
• Hands-on experience with emulation platforms like Palladium, Protium, or FPGA.
• English: Excellent verbal and written communication skills (C1) are required.

Nice to have

• Experience with UVM and verification frameworks.
• Knowledge of Qemu, Gem5, or other system emulation projects.
• Proficiency in multi-language environments (SV, C/C++, Python).
• Exposure to AI/ML techniques applied to verification or tooling.