Senior Digital IP Design Engineer (AI/ML)

TL;DR

Senior Digital IP Design Engineer (AI/ML): Developing digital IP and logic designs for complex Mixed-Signal SoCs with an accent on RTL design, microprocessor architecture, and AI/ML accelerators. Focus on optimizing area and power, implementing AMBA protocols, and ensuring functional correctness through synthesis and timing analysis.

Location: Munich, Germany

Company

hirify.global is a global leader in secure connectivity solutions for embedded and connected devices, serving automotive, industrial, and IoT markets.

What you will do

• Develop and implement digital IP and logic designs for Mixed-Signal SoCs based on architectural specifications.
• Create high-quality, area-optimal, and low-power RTL designs using Verilog and SystemVerilog.
• Perform critical design quality checks, including Lint, CDC/RDC, and timing analysis.
• Conduct IP-level design verification, simulation, and debugging to ensure functional correctness.
• Collaborate with hardware, software, and system engineering teams to define features and interfaces.
• Ensure design implementation adheres to Design for Testability (DFT) requirements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Minimum 5 years of experience in IP or subsystem design.
• Hands-on experience with CPU design, specifically RISC-V, proprietary cores, or AI/ML accelerators.
• Advanced knowledge of Verilog, SystemVerilog, and C/C++.
• Proficiency in AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR).
• Experience with scripting languages such as Python, Perl, TCL, or Shell.
• English: C1+ required (excellent written and verbal communication).

Nice to have

• Basic conversational German.
• Experience using AI-based tools to enhance development and design efficiency.