Digital Design Engineer (VLSI)

TL;DR

Digital Design Engineer (VLSI/RTL): Developing and verifying high-performance digital IPs for analog mixed-signal semiconductor solutions with an accent on RTL coding, synthesis, and timing closure. Focus on building advanced verification environments, conducting CDC/RDC checks, and performing hardware verification using FPGA kits.

Location: Cairo, Egypt (Onsite)

Company

Mixel, a hirify.global company, is an innovator of high-performance analog mixed-signal semiconductor IPs powering Mobile, Automotive, and AI applications.

What you will do

• Develop digital IPs using Verilog RTL coding, synthesis, and simulation.
• Create advanced verification environments and test-bench components.
• Conduct RTL linting, CDC/RDC checks, and formal verification as part of the sign-off flow.
• Perform synthesis and timing analysis, collaborating with physical design teams on DFT and timing closure.
• Verify digital modules using cutting-edge FPGA kits.
• Execute gate-level verification of digital IPs.

Requirements

• Bachelor’s degree in Electronics Engineering (M.Sc. is a plus).
• 0-3 years of experience in VLSI Digital Design/Verification.
• Strong knowledge of Verilog RTL design and simulation.
• Knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques.
• Understanding of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
• Solid understanding of static timing analysis (STA) and timing constraints (SDC).

Nice to have

• Familiarity with System Verilog and UVM.
• Experience with Unix/Linux operating systems.
• Knowledge of shell scripting or other programming languages.

Culture & Benefits

• Competitive pay with annual and spot bonuses.
• Long-term incentive plan awards (RSUs).
• Comprehensive health benefits.
• Paid holidays and time off.
• Access to various learning and leadership opportunities.