Назад
Company hidden
обновлено 8 часов назад

Hardware & Silicon Validation, Senior Staff Engineer (PCIe/Ethernet PHY)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Hardware & Silicon Validation, Senior Staff Engineer (PCIe/Ethernet PHY): Validating Marvell's in-house PCIe/Ethernet PHY IP in post-silicon environments, including silicon bring-up, high-speed signal measurements, and protocol debugging with an accent on SERDES characterization, eye diagrams, jitter, and BER analysis. Focus on designing and executing PHY validation plans, troubleshooting failures with advanced lab equipment and software tools, and collaborating with cross-functional teams, vendors, and customers to resolve hardware issues.

Location: Hsinchu, Taiwan

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, and data infrastructure applications.

What you will do

  • Own the post-silicon validation of PCIe/Ethernet PHY IP, including defining, documenting, executing, and reporting validation and test plans.
  • Perform lab-based silicon bring-up and unit testing for PCIe/Ethernet physical and PCS layers, firmware functionality, and relevant PCIe protocol layers.
  • Validate high-speed signals and analyze eye diagrams, jitter, and BER using oscilloscopes, BERTs, network analyzers, and other test equipment.
  • Diagnose and debug PHY and storage-interface protocol issues using software tools, hardware analyzers, logic analyzers, and protocol analyzers.
  • Lead technical discussions and collaborate with cross-functional teams, external vendors, and customers to resolve post-silicon and customer issues.

Requirements

  • 8–10 years of experience in high-speed I/O testing, debugging, and validation.
  • Strong understanding of high-speed SERDES, equalization techniques, and PCIe protocols.
  • Hands-on experience with system bring-up, system testing, and laboratory debugging.
  • In-depth knowledge of SERDES characterization equipment, including scopes, BERTs, and network analyzers.
  • Experience developing validation automation and performing data analysis with Python, MATLAB, or similar scripting languages.
  • Excellent written and spoken English communication skills. A bachelor’s degree in electrical engineering with 8–10 years of relevant experience, or a master’s degree with 6–8 years of relevant experience, is required.

Nice to have

  • Knowledge of PCIe, Ethernet, or SAS/SATA SERDES.
  • Understanding of PIPE, PCS, MAC, and physical and protocol layers of high-speed interfaces.
  • Board design knowledge, including the ability to read schematics and board layouts.
  • Knowledge of SERDES modeling techniques.

Culture & Benefits

  • Competitive compensation and benefits.
  • Collaborative, transparent, and inclusive work environment.
  • Resources and support for professional growth and development.
  • Work focused on semiconductor technologies used by internal and external customers worldwide.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills.
  • AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.
  • Access to export-controlled technology may require an export license review before employment.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →