Senior Staff Design Engineer (PCIe/CXL)

TL;DR

Senior Staff Design Engineer (PCIe/CXL): Designing and implementing high-performance PCIe/CXL subsystem building blocks for hyperscale cloud and AI custom chips with an accent on RTL implementation and micro-architecture definition. Focus on translating architectural requirements into robust RTL, optimizing data paths, and ensuring seamless SoC integration using AMBA protocols.

Location: Santa Clara, CA

Salary: $134,390 - $201,300 per annum

Company

hirify.global is a semiconductor leader providing essential data infrastructure building blocks across enterprise, cloud, and AI architectures.

What you will do

• Own and drive PCIe/CXL subsystem micro-architecture definition, RTL implementation, and integration.
• Translate complex architecture requirements into robust, production-ready RTL designs.
• Collaborate with Design Verification teams on test-plan reviews, debug, and coverage closure.
• Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug in coordination with firmware and validation teams.
• Mentor junior designers and provide technical leadership within the PCIe/CXL domain.

Requirements

• Must be eligible to access export-controlled information as defined under applicable U.S. law.
• Master's or Bachelor's degree in Electronics/Electrical Engineering with 10+ years of RTL design experience.
• Proven experience delivering complex PCIe/CXL controllers or subsystems from architecture to RTL closure.
• Strong hands-on expertise in System Verilog / Verilog RTL development.
• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Proficiency in scripting (TCL, Perl, Python) and version control systems (GIT, SVN).

Nice to have

• Experience with end-to-end PCIe/CXL subsystem RTL design execution and sign-off.
• Experience designing high-performance, low-latency data paths with complex ordering and coherency.
• Proficiency in debugging functional and performance issues at the subsystem and SoC levels.
• Familiarity with post-silicon bring-up and debug methodologies.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate contributions and milestones.