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5 дней назад

Director of Silicon Design for MEM/PCIE COE

185 390 - 277 700$
Тип работы
fulltime
Грейд
director
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR

Director of Silicon Design for MEM/PCIE COE (PCIe/CXL, Memory): Define and scale RTL development and own end-to-end PCIe/CXL and Memory subsystem RTL design execution and sign-off with an accent on physical design convergence, power/performance optimization, and predictable tape-out readiness. Focus on leading distributed RTL design teams, resolving cross-program technical escalations, and ensuring A0 silicon production for complex SoCs.

Location: Santa Clara, CA

Salary: $185,390 - $277,700 per annum

Company

hirify.global develops semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

  • Define and scale RTL development, driving reuse across IP and programs.
  • Own end-to-end PCIe/CXL and Memory subsystem RTL design execution and sign-off.
  • Collaborate with architecture, DV, firmware, SoC, and post-silicon teams to influence specifications early and reduce downstream risk.
  • Manage distributed RTL design teams and develop technical depth and future leaders.
  • Own design schedules, risk assessment, physical design closure, and communicate tape-out readiness to senior management and stakeholders.
  • Review and resolve cross-program technical issues and escalations; engage ecosystem partners (JEDEC, IP vendors, PHY providers) for interoperability and enablement.

Requirements

  • BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering with 10-15 years of relevant experience.
  • Proven experience delivering complex PCIe/CXL and/or Memory subsystems from architecture through RTL closure.
  • Strong SystemVerilog RTL development experience, including physical design convergence, power/performance optimization, and silicon bring-up.
  • Experience with EDA verification/debugging tools, scripting (Python or Perl), and revision control systems.
  • Strong understanding of PCIe/CXL architectures and memory technologies (DDR, LPDDR, HBM).
  • Proven track record owning complex subsystems end-to-end across multiple products and leading distributed teams across sites.

Culture & Benefits

  • Comprehensive benefits covering financial well-being, family support, mental and physical health, and recognition.
  • Employee stock purchase plan with a 2-year look back.
  • Family support programs to balance work and home life.
  • Robust mental health resources and recognition/service awards.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication in real time.
  • AI tools are not permitted during interviews and may lead to disqualification.

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