Analog Design Engineering Manager (Hardware)

TL;DR

Analog Design Engineering Manager (Hardware): Leading technical teams in the development of high-speed analog and mixed-signal IP for hirify.global's client, datacenter, and foundry products with an accent on IO and chiplet interconnect technology. Focus on driving technical excellence in circuit design, managing complex project execution, and mentoring a team of analog engineers to deliver high-quality silicon solutions.

Location: Must be based in the US (Phoenix, AZ or Hillsboro, OR). This is an on-site role requiring office presence at least 4 days per week.

Salary: $220,920–$311,890 USD

Company

hirify.global is a global leader in semiconductor manufacturing and technology, building scalable engineering solutions across product enablement, custom ASIC, and foundry services.

What you will do

• Lead and mentor a team of 10-15 analog design engineers through all phases of IP development.
• Guide the design of analog circuits including ADCs, DACs, and voltage regulators.
• Create detailed execution plans and manage schedules, resources, and dependencies for IP milestones.
• Drive efficiency in the development cycle through the adoption of automated and AI-supported solutions.
• Collaborate cross-functionally with architecture, physical design, and post-silicon validation teams.
• Ensure high-quality silicon delivery from concept to launch and post-silicon debug.

Requirements

• Bachelor's degree in Electrical or Electronics Engineering with 12+ years of experience.
• 8+ years of experience in a management or leadership role.
• Proven expertise in analog IP development and silicon bring-up.
• Solid foundational knowledge of analog design principles including noise, jitter, and stability.
• Excellent communication and presentation skills for technical and executive audiences.
• Must be eligible to work in the US and pass an extended background investigation.

Nice to have

• PhD or Master's degree in Electrical or Electronics Engineering.
• Hands-on design experience with PLL, CDR, CTLE, DFE, or Transmitter/Receiver design.
• Deep knowledge of high-speed serial IO technologies like PCIe/CXL and die-to-die technologies like UCIe.

Culture & Benefits

• Competitive total compensation package including pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Opportunity to work on industry-defining technology for AI and datacenter customers.
• Collaborative environment with global engineering teams.