Senior SoC Compute/Memory Subsystem Architect

TL;DR

Senior SoC Compute/Memory Subsystem Architect: Define and drive end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms with an accent on system-level performance, scalability, power efficiency, and programmability. Focus on designing compute/cache/coherency/memory and virtualization (SMMU/IOMMU) architectures and integrating compute with networking, storage, and accelerator subsystems in hyperscale environments.

Location: US, California, Santa Clara

Salary: $164,470.00–$269,100.00 USD (annual)

Company

hirify.global’s Central Engineering Group (CEG) builds scalable engineering solutions across product enablement, custom ASIC, and foundry enablement.

What you will do

• Define compute subsystem architecture for IPU compute complexes, including core selection, scaling strategy, and configuration tradeoffs.
• Architect multi-level cache hierarchies and coherency models across compute cores, accelerators, and IO subsystems.
• Architect memory subsystems (DDR/LPDDR interfaces, memory controllers, scheduling/QoS, bandwidth provisioning and scaling) and memory access models.
• Define IO memory and virtualization architecture using SMMU/IOMMU, including multi-tenant isolation and shared vs isolated memory models.
• Drive system-level integration across compute, networking packet processing pipelines, storage, and accelerator subsystems to optimize data movement.
• Lead multi-generation compute/memory roadmap and cross-functional architecture alignment across networking, SoC fabric, firmware/OS/drivers, and validation/performance modeling.

Requirements

• BS degree in Electrical Engineering, Computer Engineering, or a STEM-related field.
• 7+ years of experience in SoC/CPU/memory subsystem architecture, including CPU architecture and cache hierarchies.
• Experience with memory subsystems (DDR/HBM, controllers, QoS) and coherent/non-coherent interconnect architectures.
• Experience with system-level performance and PPA tradeoff analysis.
• Ability to drive architecture definition from concept to silicon.
• Hybrid work model with on-site time at an assigned hirify.global site in the US (primary location: Santa Clara, CA).

Nice to have

• Postgraduate degree in Electrical Engineering, Computer Engineering, or a STEM-related field.
• ARM and x86 compute/memory subsystem experience, including NUMA, cache coherency, or large-scale platform architectures.
• Experience with IPU/SmartNIC or accelerator-centric SoCs in cloud/hyperscale environments.
• Familiarity with PCIe, CXL, and memory semantics for high-performance IO.
• Track record of multi-generation architectural ownership and mentoring other architects.

Culture & Benefits

• Hybrid work model: split time between on-site at an assigned hirify.global site and off-site.
• Total compensation package including competitive pay, stock bonuses, and benefits (health, retirement, vacation).
• Immigration sponsorship may be available per hirify.global guidelines.

Hiring process

• Application review for minimum qualifications and experience fit.
• Interviews to evaluate architecture depth, cross-functional leadership, and system-level tradeoff thinking.
• Compensation range details shared for the preferred US work location during the hiring process.