Analog Design Engineer (AI)

TL;DR

Analog Design Engineer (AI): Developing cutting-edge die-to-die chiplet PHY IP solutions for AI computing platforms with an accent on deep sub-micron FinFET technologies. Focus on designing high-speed SerDes, PLLs, and mixed-signal blocks, managing the full lifecycle from architecture to silicon bring-up.

Location: Must be based in North America

Compensation: $100,000–$500,000

Company

hirify.global is a next-generation computing company building high-performance AI platforms and RISC-V CPUs.

What you will do

• Develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks.
• Own the full design lifecycle from architecture and circuit design to layout interaction and tape-out.
• Collaborate with cross-functional teams including digital, verification, and software to integrate AMS IP.
• Perform silicon bring-up and testing to ensure production-quality results.
• Optimize circuits for performance, power, and area in advanced FinFET nodes.

Requirements

• Must be based in North America
• 10+ years of analog/mixed-signal IC design experience in FinFET.
• Deep expertise in high-speed datacomm/SerDes and die-to-die PHY design (Tx/Rx, DDR, PCIe, USB).
• Proven track record in production tape-outs and silicon bring-up.
• Must be eligible to access U.S. export-controlled technology
• MSEE/PhD or equivalent background.

Culture & Benefits

• Competitive compensation package including base and variable targets.
• Opportunity to work on industry-leading AI hardware and RISC-V architecture.
• Collaborative environment focused on solving complex semiconductor challenges.
• Equal opportunity employer with a commitment to innovation.