Senior FPGA Design Engineer (Verilog/SystemVerilog)

TL;DR

Senior FPGA Design Engineer (Verilog/SystemVerilog): Designing and implementing complex RTL logic for ASIC and FPGA projects with an accent on high-speed serial interfaces, timing closure, and backend synthesis. Focus on solving complex asynchronous clock boundary challenges, performing system-level lab bring-up, and integrating industry-standard interfaces.

Location: Searching globally; headquartered in Ottawa, Canada

Salary: $120,000 – $170,000

Company

hirify.global specializes in ASIC and FPGA design, verification, and embedded software development services to augment client teams.

What you will do

• Translate high-level requirements into detailed technical specifications.
• Design and implement RTL logic using Verilog or SystemVerilog.
• Execute FPGA synthesis, backend processes, and timing closure.
• Perform lab bring-up, product integration, and system-level troubleshooting.
• Provide technical support to customers to resolve complex technical issues.

Requirements

• Minimum 5 years of relevant experience in FPGA design.
• Proficiency in high-speed FPGA Design Flow using Verilog and SystemVerilog.
• Expertise with Xilinx Vivado or Intel Quartus and recent device families.
• Experience with complex asynchronous clock boundaries and high-speed serial interfaces.
• Practical experience in lab environments for system-level troubleshooting.
• Knowledge of industry standard interfaces (e.g., Ethernet, PCIe, SPI, I2C, USB, AMBA).

Nice to have

• Experience with test verification and scripting.
• Background in software development.

Culture & Benefits

• Competitive compensation with company bonus and benefits plan.
• Opportunity to work in an adaptable and efficient team environment.
• Focus on technical excellence and acceleration of complete design development.