Analog IP Design Execution Manager (Semiconductor)

TL;DR

Analog IP Design Execution Manager (Semiconductor): Leading technical teams to deliver high-speed serial IO and die-to-die interfaces for hirify.global's product and foundry businesses with an accent on end-to-end IP planning, execution, and silicon lifecycle management. Focus on driving cross-functional collaboration, mitigating technical risks, and ensuring on-time delivery of complex mixed-signal IP in advanced process nodes.

Location: Must be based in the US (Phoenix, AZ; Santa Clara, CA; or Hillsboro, OR). This is a hybrid role requiring at least 4 days per week on-site.

Salary: $190,610–$269,100 USD

Company

hirify.global is a global leader in semiconductor technology, building scalable engineering solutions across product enablement, custom ASIC, and foundry services.

What you will do

• Lead integrated IP planning, execution, and delivery from conceptual planning to post-silicon validation.
• Coordinate across architecture, analog, logic, and validation domains to meet project milestones.
• Identify technical problems and drive solutions using data-driven metrics and trends.
• Ensure progress against schedules and recommend recovery actions for complex dependencies.
• Communicate program status and risks to stakeholders ranging from engineers to executives.
• Conduct retrospective reviews to drive continuous improvements in execution efficiency and quality.

Requirements

• Bachelor's degree in Electrical or Electronics Engineering with 8+ years of experience.
• 5+ years of experience managing technical execution for silicon projects.
• Solid foundational knowledge of analog design principles including noise, jitter, stability, and linearity.
• Proven experience executing complex mixed-signal or high-speed serial IP development in advanced semiconductor process nodes.
• Ability to work on-site at an hirify.global facility at least 4 days per week.
• Excellent communication and presentation skills for diverse technical and executive audiences.

Nice to have

• Master's degree in Electrical or Electronics Engineering.
• Deep knowledge of high-speed serial IO technologies (PCIe/CXL, USB) and die-to-die technologies (UCIe, BoW, HBM).
• Experience in silicon bring-up, post-silicon validation, and lab debug.
• Familiarity with AI/ML-driven design productivity techniques and automation frameworks.

Culture & Benefits

• Competitive total compensation package including base pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model supporting flexibility between on-site and off-site work.
• Opportunity to work on industry-defining technology for major client, datacenter, and foundry customers.